Architecture for a physical interface of a high speed front side bus
US7945805B2 · kind B2 · utility
7Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2007 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Dec 16, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.