System and method for managing memory errors in an information handling system
US7945815B2 · kind B2 · utility
7Cited by
51References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2007 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Nov 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for handling memory defects during the POST phase and memory calibration in single processor and multiprocessor information handling systems is disclosed whereby information regarding the location of a known memory defect is utilized to optimize the performance of an information handling system. Memory defects within system memory are identified and replaced during operation with error free memory space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.