Programmable address space built-in self test (BIST) device and method for fault detection
US7945823B2 · kind B2 · utility
4Cited by
17References
17Claims
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Key dates
| Filing date | Mar 2, 2007 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Oct 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A built-in self-test (BIST) circuit for testing addressable locations can include a BIST generator (202) that can generate test addresses for testing each addressable location. Defective addresses can be stored in a fault address store (216). An address range selector circuit (230) can limit the range of addresses generated by an address generator (234). Once defective addresses for a first range have been detected, an address range selector circuit (230) can test another range. An entire address range can thus be tested regardless of the depth of a fault address store (216).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.