Patent · US Active

Semiconductor integrated circuit

US7945829B2 · kind B2 · utility

2Cited by

9References

6Claims

0Family size

Assignee

NATIONAL UNIVERSITY CORPORATION CHIBA UNIVERSITY · JP

Inventors

Kazuteru Nanba · Chiba, JP
Hideo Ito · Akishima, JP

Key dates

Filing date	Jan 5, 2006
Grant date	May 17, 2011
Priority date	—
Expiry date	Aug 15, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH03K3/3562
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

[PROBLEMS] To provide a semiconductor integrated circuit by which what has been referred to as two-pattern test is made possible without greatly increasing an occupying area. [MEANS FOR SOLVING PROBLEMS] The semiconductor integrated circuit is provided with a plurality of flip-flop circuits and selectors corresponding to each flip-flop circuit. Each flip-flop circuit is provided with a master latch and a slave latch connected to the master latch. The selector is electrically connected with the master latch of the flip-flop circuit to which the selector corresponds, and is also connected with the master latch of the flip-flop circuit other than the one to which the selector corresponds.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.