Parity check decoder architecture
US7945838B2 · kind B2 · utility
0Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 4, 2007 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Mar 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1111
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.