Method for realizing an electric linkage in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components
US7945867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Sep 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components. The method includes: providing a nanometric circuit architecture comprising a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above the succession, an insulating layer; opening, in the insulating layer, a window of nanometric width b extended along a direction inclined by an angle α with respect to the direction x to substantially cross the whole succession of nanowires, with exposure of a succession of exposed portions of the nanowires, one for each nanowire; realizing, above the insulating layer, a plurality of conductive dies extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies overlapping said window onto a respective exposed portion of a nanowire with obtainment of a plurality of contacts realizing said electric connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.