Tunable integrated circuit design for nano-scale technologies
US7945868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2008 |
| Grant date | May 17, 2011 |
| Priority date | — |
| Expiry date | Nov 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention discloses a method for tuning nano-scale analog-circuit designs in order to reduce random-device mismatches and optimize said design, where nano-scale devices potentially have large-scale process variations. The method includes providing a tunable circuit topology, wherein each nano-scale device comprises a single component or comprises multiple parallel components. Each component is decomposed into multiple discrete sub-components, wherein each said sub-component either operates in parallel with other like components to effectively operate like one bigger component. The sub-components are subjected to a dynamic-programming process to adaptively select the sub-components to be kept operational, while configuring the nonselected sub-components to be nonoperational, based on the measurement of at least one operational parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.