Patent · US Active

Constraint based retiming of synchronous circuits

US7945880B1 · kind B1 · utility

24Cited by

12References

27Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Christoph Albrecht · San Jose, US
Sascha Richter · Munich, DE

Key dates

Filing date	May 30, 2007
Grant date	May 17, 2011
Priority date	—
Expiry date	Jan 14, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment of the invention, a method of retiming a circuit is disclosed. The method includes computing an upper bound and a lower bound for a clock period of a clock signal to clock a circuit in response to a netlist of the circuit; selecting a potential clock period for the clock signal to clock registers of the circuit in response to the computed upper bound and the computed lower bound for the clock period; computing an upper bound and a lower bound of a retiming value for each node of the circuit to determine if a retiming of the circuit is achievable with the potential clock period; and computing the retiming value for each node of the circuit to minimize circuit area in response to the computed upper bound and the computed lower bound of the retiming value for each node.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.