Thin film transistor array panel for a display device and a method of manufacturing the same
US7947539B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2009 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Aug 27, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using photolithography; ashing and partially removing a photoresist film pattern used in the patterning of the etch stop and semiconductor layers; etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing ohmic contact and data metal layers onto the etch stop members, etching the ohmic contact and data metal layers at the same time using photolithography to form data lines having source and drain electrodes, and ohmic contact members below the source and drain electrodes; forming a passivation layer on the data lines and drain electrodes; and forming pixel electrodes on the passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.