Thin film transistor array substrate and manufacturing method thereof
US7948570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jul 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/1368
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A thin film transistor (TFT) array substrate for a liquid crystal display comprises a gate line and a data line formed in a display region, a gate connecting line and a data connecting line formed in a PAD region, and a TFT formed at an intersection between the gate line and the data line. The TFT comprises a gate electrode on a base substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a doped semiconductor layer on the semiconductor layer, and a source electrode and a drain electrode that are on the doped semiconductor layer, and a TFT channel is defined in the semiconductor layer between the source electrode and the drain electrode. The array substrate further comprises a passivation layer that is formed on the source electrode and the drain electrode and a pixel electrode, a portion of which is formed under the drain electrode and connected with the drain electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.