Systems and methods for controlling data equalization
US7948702B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jul 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2220/2516
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present invention provide systems and methods for performing data equalization. For example, various embodiments of the present invention provide data equalization circuits that include an equalization circuit and a transition adjustment circuit. The equalization circuit receives a series of at least two original data bits and replaces at least one of the two original data bits with an equalization pattern including two or more equalization bits. The original data bits correspond to an original data clock, and the two or more equalization bits correspond to an equalization data clock. The transition adjustment circuit is operable to modify an occurrence of a transition from one logic state to another logic state within the equalization pattern on a sub-equalization data clock basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.