Semiconductor memory device having vertical transistors
US7948784B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Nov 24, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.