Semiconductor memory device
US7948790B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2009 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Dec 24, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell arranged between first and second wirings includes a variable-resistor element. A controller controls a voltage applied between the first and second wirings. The controller performs a first operation that applies a first voltage between the first and second wirings to switch the variable-resistor element from a first state with a resistance value not less than a first resistance value, to a second state with a resistance value not more than a second resistance value smaller than the first resistance value. The second operation applies a second voltage smaller than the first voltage between the first and second wirings to switch the variable-resistor element from the second state to the first state. In the first operation, a verify voltage is applied between the first and second wirings. Based on the obtained signal, a third voltage smaller than the first voltage is applied between the first and second wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.