Patent · US Active

Memory and techniques for using same

US7948792B1 · kind B1 · utility

11Cited by

27References

22Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Andy L. Lee · San Jose, US
Lu Zhou · Santa Clara, US

Key dates

Filing date	Apr 15, 2009
Grant date	May 24, 2011
Priority date	—
Expiry date	Nov 18, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

There are provided methods and devices for providing overdrive voltages to address lines to help prevent leakage current in semiconductor memories, such as configuration memories used with programmable logic devices. Specifically, for example, there is provided a memory that includes an array of memory cells. Each memory cell includes a retainer circuit. An access transistor is coupled to the retainer circuit. An overdrive voltage level may be applied to the access transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.