Data slicer circuit, demodulation stage, receiving system and method for demodulating shift key coded signals
US7949075B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/1563
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention relates to a data slicer circuit for processing a voltage signal input having two voltage values, each value representative of a value assigned to one characteristic of a modulated baseband carrier signal corresponding to a binary one or zero bit of information, the data slicer comprising first means for detecting a rising transition segment of the voltage signal, first means for detecting a falling transition segment of the voltage signal, means for providing a first serial digital signal output with a binary zero value if a rising transition segment of the voltage signal is detected or a binary one value if a falling transition segment of the voltage signal is detected or vice versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.