Architecture and instruction set for implementing advanced encryption standard (AES)
US7949130B2 · kind B2 · utility
53Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2006 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Feb 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.