Implementation of decimation filter in integrated circuit device using ram-based data storage
US7949699B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2007 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Mar 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2218/085
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.