Modal interval processor
US7949700B2 · kind B2 · utility
1Cited by
9References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 5, 2006 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jul 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit computes various modal interval (MI) arithmetic values using a plurality of arithmetic function units (AFUs), each dedicated to compute a specific MI arithmetic operation. The AFUs receive first and second MI operand values each encoded in first and second operand signals. Each AFU provides a MI result value encoded in a result signal to a multiplexer. The multiplexer receives a selector signal specifying the MI arithmetic operation desired, and provides to a result register, an output signal encoding the MI result value specified by the selector signal. The result register stores the MI result value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.