Two dimensional addressing of a matrix-vector register array
US7949853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Nov 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.