Inter-port communication in a multi-port memory device
US7949863B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2007 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Feb 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.