Microelectronic device and pin arrangement method thereof
US7949919B2 · kind B2 · utility
4Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2008 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Dec 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3172
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention provides a microelectronic device with a circuit core and a boundary scan test interface sharing a number of pre-selected pins. In the mode of a boundary scan test, the boundary scan test interface manipulates the input and output of the test signal through the shared pins. Pins necessary for the microelectronic device are therefore reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.