Strengthening parity check bit protection for array-like LDPC codes
US7949932B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | May 24, 2011 |
| Priority date | — |
| Expiry date | Jan 11, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LDPC parity check matrix originated using an array code provides more protection against errors for parity bits 1 through 1−p, which can, during decoding, allow faster convergence to a higher LLR value for those bits as well as higher overall reliability of other parity check bits. The present parity check matrix provides an upper triangular sub-matrix (H1) for the parity check bits, where column weights for parity bits 1 through p−1 can be greater than 1. Aspects include encoders to encode user bits using the parity check matrix, decoders to decode based on the parity check matrix, systems comprising encoders and/or decoders, encoder and decoder methods; as well as computer readable media comprising programs for implementing such methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.