Method of fabricating non-volatile memory device having separate charge trap patterns
US7951671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | May 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A method of fabricating a non-volatile memory device includes forming an isolation trench in a semiconductor substrate, and the isolation trench defines first and second fins. The method further includes forming an isolation layer partially filling the isolation trench, forming first and second charge trap patterns respectively covering parts of the first and second fins projecting from the isolation layer, and forming a control gate electrode covering the first and second charge trap patterns and crossing the first and second fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.