Method for fabricating a SONOS memory
US7951674B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Dec 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
The present invention provides a method for making SONOS memory, comprising the following steps: depositing silicon oxide layer and silicon oxynitride layer in sequence on underlayer; coating a layer of photoresist on the silicon oxynitride layer; removing part of the photoresist and form the logic area; removing silicon oxynitride layer in the logic area; removing the bottom oxide layer in the logic area; growing top oxide layer on the silicon oxynitride layer and logic area; removing the top oxide layer in the logic area; growing gate oxide layer; forming device structure of SONOS and logic area. The present invention can avoid the damage of top oxide layer and lateral etching in wet etching so as to improve the defect-free rate of devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.