Bias circuit for common-mode and semiconductor process voltage and temperature optimization for a receiver assembly
US7952398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2007 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Mar 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B3/30
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the receiver assembly. A bias signal directs the bridge circuit over a set of worst case conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.