Phase lock loop circuit
US7952436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Aug 25, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop (PLL) circuit is provided. A voltage controlled oscillator (VCO) generates an output clock signal based on a control voltage. A controller provides a first digital control word, a second digital control word and a loop factor. A frequency modifier is coupled to the output clock signal, controlled by the controller to divide the output clock signal by the loop factor to generate a feedback frequency. A charge pump is controlled by the up signal and down signal to generate a charge pump current, comprising a first digital to analog converter (DAC) to generate a first current based on the first digital control word when the up signal is asserted. A second DAC generates a second current based on a second digital control word when the down signal is asserted. The controller defines a first relationship between the first digital control word and the loop factor, and the controller defines a second relationship between the second digital control word and the loop factor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.