No-disturb bit line write for improving speed of eDRAM
US7952946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Apr 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.