Concurrent input/output control and integrated error management in FIFO
US7953907B1 · kind B1 · utility
3Cited by
32References
33Claims
0Family size
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Key dates
| Filing date | Aug 16, 2007 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.