Interrupt dispatching method in multi-core environment and multi-core processor
US7953915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2009 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Jun 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/505
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.