Architecture for joint detection hardware accelerator
US7953958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Dec 30, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70711
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.