Processor
US7953959B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2006 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Mar 30, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes: an instruction buffer which holds a group of instructions that can be executed in parallel; an instruction decoding unit which decodes part or all of the group of instructions; and an instruction issuance control unit which detects whether or not a factor obstructing simultaneous execution of the group of instructions exists in the group of instructions and supplies the group of instructions to the instruction decoding unit by controlling the instruction buffer so that the instructions of the group of instructions are sequentially supplied when the factor exists and all the instructions of the group of instructions are simultaneously supplied when the factor does not exist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.