Secure transaction microcontroller with tamper control circuitry
US7953989B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2008 |
| Grant date | May 31, 2011 |
| Priority date | — |
| Expiry date | Aug 15, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/922
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high security microcontroller (such as in a point of sale terminal) includes tamper control circuitry for detecting vulnerability conditions: a write to program memory before the sensitive financial information has been erased, a tamper detect condition, the enabling of a debugger, a power-up condition, an illegal temperature condition, an illegal supply voltage condition, an oscillator fail condition, and a battery removal condition. If the tamper control circuitry detects a vulnerability condition, then the memory where the sensitive financial information could be stored is erased before boot loader operation or debugger operation can be enabled. Upon power-up if a valid image is detected in program memory, then the boot loader is not executed and secure memory is not erased but rather the image is executed. The tamper control circuitry is a hardware state machine that is outside control of user-loaded software and is outside control of the debugger.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.