Digital lock detector and frequency synthesizer using the same
US7956658B2 · kind B2 · utility
1Cited by
5References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 28, 2009 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Oct 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.