Low-noise DC offset calibration circuit and related receiver stage
US7956680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2010 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Apr 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/30
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A DC offset calibration circuit has a first resistor, a first switch, a second resistor, and a second switch. The first resistor is coupled to a first supply voltage. The first switch is coupled to the first resistor, to a first input of an amplifier, and to a first input resistor. A second end of the first input resistor is not coupled to the first supply voltage. The second resistor is coupled to a second supply voltage. The second switch is coupled to the second resistor, to a second input of the amplifier, and to a first end of a second input resistor. A second end of the second input resistor is not coupled to the second supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.