Patent · US Active

Read and volatile NV standby disturb

US7957192B2 · kind B2 · utility

1Cited by

2References

15Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Andreas Scade · Dresden, DE
Stefan Guenther · Lake Orion, US
Jeong-Mo Hwang · Jicheon-myeon, KR

Key dates

Filing date	Dec 31, 2007
Grant date	Jun 7, 2011
Priority date	—
Expiry date	Jun 24, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/0466
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.