Methods and apparatuses to effect a variable-width link
US7957428B2 · kind B2 · utility
13Cited by
10References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2004 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.