Enhanced signaling sensitivity using multiple references
US7957472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 7, 2007 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Mar 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver circuit uses two or more comparators to detect the received data signal. Each comparator is set to compare the data signal to a different reference signal. The output signals of the comparators are received into a detector circuit, which provides a third output signal that establishes the logic state of the received signal based on whether or not the output signals of the comparators are equal. Depending on the logic state of the data signal, one of the comparators provides its output signal sooner than the other. Each comparator may be implemented by a differential amplifier. In one embodiment, the reference signals are threshold voltages which may be provided by the tripping voltages at the trip points for the logic HIGH and LOW states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.