Address translation system for use in a simulation environment
US7957951B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Feb 7, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for simulation of a testable system are provided in which a virtual testable system is used. One method includes inputting a system definition file into a translation utility, where the system definition file includes a plurality of physical addresses required for execution of the system definition file in the testable system. The method also includes inputting a memory map file into the translation utility, the memory map representing a virtual memory space for a virtual testable system. The method further includes generating virtual translation information by translating the physical addresses into virtual addresses using the memory map file.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.