Patent · US Active

Coherency maintaining device and coherency maintaining method

US7958318B2 · kind B2 · utility

2Cited by

4References

12Claims

0Family size

Assignee

FUJITSU LIMITED · JP

Inventors

Hideki Sakata · Nishinomiya, JP
Hiroyuki Kojima · Hiratsuka, JP
Masaki Ukai · Kawasaki, JP

Key dates

Filing date	Aug 14, 2008
Grant date	Jun 7, 2011
Priority date	—
Expiry date	Oct 12, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0864
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.