Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
US7958333B2 · kind B2 · utility
6Cited by
1References
31Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 30, 2007 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Nov 24, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.