Highly threaded static timer
US7958474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2008 |
| Grant date | Jun 7, 2011 |
| Priority date | — |
| Expiry date | Sep 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.