Tuning capacitance to enhance FET stack voltage withstand
US7960772B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2007 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Mar 26, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49105
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.