Multi-valued mask ROM

US7960777B2 · kind B2 · utility

Assignee

• RENESAS ELECTRONICS CORPORATION · JP

Inventor

• Takayuki Onda · Yokohama, JP

Key dates

• Filing date: Oct 2, 2008
• Grant date: Jun 14, 2011
• Expiry date: Oct 29, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/34

Abstract

A mask ROM is provided with a plurality of memory cells each including first and second nodes, and a transistor having a source and drain connected to the first and second nodes, respectively. A first memory cell out of the plurality of memory cells further includes a first resistive interconnection which provides an electrical connection between the first and second nodes. The resistance of the first resistive interconnection is adjusted depending on data stored onto the first memory cell.