Chip arrangement and method of manufacturing a chip arrangement

US7960843B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Harry Hedler · Germering, DE
• Roland Irsigler · Munich, DE

Key dates

• Filing date: Jun 16, 2009
• Grant date: Jun 14, 2011
• Expiry date: Nov 18, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/181
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side.