Amplifier with compensated gate bias
US7961049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2006 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Dec 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/451
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier circuit includes an amplifier stage (10) having an amplifier transistor (104) with a gate coupled to an input (100) of the amplifier stage, a source coupled to a reference connection (gnd) and a drain coupled to a positive power supply connection (V+). The amplifier circuit includes a bias stage (12) having a bias transistor (120), a drain resistance (124) and a source resistance (122). The bias transistor includes a gate coupled to a negative power supply connection (V−), a source coupled to the negative power supply connection (V−) via the source resistance and a drain coupled to the reference connection via the drain resistance and to the gate of the amplifier transistor. The bias stage includes a further resistance (20, 22) coupled from a node between the source of the bias transistor and the source resistance of the bias transistor to a circuit node that carries a voltage higher than the voltage at the negative power supply connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.