Timing recovery for partial-response maximum likelihood sequence detector

US7961054B2 · kind B2 · utility

Assignee

• Menara Networks, Inc. · US

Inventors

• Jomo K. Edwards · Aliso Viejo, US
• Christopher A. Gill · Orange, US
• Devin Ng · Mission Viejo, US
• Harry Tan · Rancho Palos Verdes, US
• Salam Elahmadi · Dallas, US
• Matthias Bussman · Los Angeles, US

Key dates

• Filing date: Oct 28, 2008
• Grant date: Jun 14, 2011
• Expiry date: Dec 20, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03L2207/06
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

An embodiment of the present invention is a technique for timing recovery. A frequency acquisition loop locks a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock. The frequency acquisition loop generates first and second feedback clocks from the VCO clock. A data lock phase loop generates a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock. The driving signal controls the multi-band VCO in a data phase lock mode. A lock detect controller detects a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock.