Method and apparatus for dithering in multi-bit sigma-delta analog-to-digital converters
US7961126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2009 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/424
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-bit (M-bit, M>1) or multi-level (nlev levels, nlev>2, encoded on M bits where M=Floor(log 2(nlev))) sigma-delta analog-to-digital converter (ADC) with a variable resolution multi-bit quantizer having its resolution (number of distinct output levels) and associated quantization thresholds changed for each voltage sample with a random or pseudo-random sequence N(n) to provide automatic dynamic dithering for removing undesired idle tones in the digital output of the sigma-delta ADC. The random integer numbers N(n) between 2 and nlev may be provided by a random or pseudo-random sequence generator, e.g., Galois linear feedback shift register in combination with digital comparators and an adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.