Multilayer chip capacitor
US7961453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2008 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Sep 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G4/232
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A multilayer chip capacitor including: a capacitor body formed of a lamination of a plurality of dielectric layers and having a bottom surface that is a mounting area; a plurality of internal electrodes disposed to be opposite to each other, interposing a dielectric layer there between in the capacitor body and having one lead extended to the bottom surface, respectively; and three or more external electrodes formed on the bottom surface and connected to corresponding internal electrodes via the leads, wherein the internal electrodes are vertically disposed on the bottom surface, and the leads of the internal electrodes having a different polarity from each other, adjacent to each other in a lamination direction, are disposed to be always adjacent to each other in a horizontal direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.