Memory power management systems and methods
US7961546B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2008 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Jan 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory power management systems and methods are provided. One embodiment of the present invention includes a memory power management system. The system comprises a first low dropout (LDO) regulator that provides an active operating voltage that is derived from a first supply voltage to power a memory array during an active mode. The system further comprises a second LDO regulator that provides a minimum memory retention voltage that is derived from a second supply voltage to power the memory array in a standby mode, wherein the second supply voltage also powers at least one peripheral circuit for reading from and/or writing to the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.