Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle
US7961559B2 · kind B2 · utility
18Cited by
28References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2009 |
| Grant date | Jun 14, 2011 |
| Priority date | — |
| Expiry date | Dec 8, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit and method for measuring duty cycle uncertainty in an on-chip global clock. A global clock is provided to a delay line at a local clock buffer. Delay line taps (inverter outputs) are inputs to a register that is clocked by the local clock buffer. The register captures clock edges, which are filtered to identify a single location for each edge. Imbalance in space between the edges indicated imbalance in duty cycle. Up/down signals are generated from any imbalance and passed to a phase locked loop to adjust the balance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.